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RE: SMP

Date1998-04-14 01:14
FromDustin Barlow
SubjectRE: SMP
Here's a couple of articles I found that I'll throw into the discussion:

http://developer.intel.com/design/pcisets/PRODBREF/29772801.HTM

http://developer.intel.com/design/agpsets/440/297855_001.htm

http://developer.intel.com/design/pcisets/PRODBREF/430TX/708.HTM

http://developer.intel.com/design/pcisets/PRODBREF/WHY_CONC.HTM

Dustin

-----Original Message-----
From:	Michael A. Thompson [SMTP:mat0001@jove.acs.unt.edu]
Sent:	Monday, April 13, 1998 1:19 PM
To:	Csound@noether.ex.ac.uk
Subject:	SMP

Yet another gross oversimplification and a misleading statement often
expressed by reporters who have very little or no understanding of what
multiprocessing is,
         and what are the bottlenecks in a computer system with more
than one CPU.

         Reality:

              Having N processors in a system is a long way away from
having the system utilize all their power. Achieving this is mainly an
operating system (software)
              issue. It is much easier to make a system with N
processors (and there are several PC vendors stuffing their boxes with
additional CPUs) than having a system
              that actually works N times faster, or close to that, by
adding more processors. If you try one of these PC based systems, and
expect doubling or tripling in
              speed, chances are you're in for a disappointment. In fact
the current Intel's SHV motherboards are known to saturate their system
bus fairly easily with
              commercial workloads (like databases) at a low count of 4
CPUs due to low memory bandwidth and relatively small (512KB) caches.

 Ran across this info on an SGI web site:
http://reality.agi.com/ariel/sgi-myths.html


"In symmetric multiprocessing (SMP), the bottleneck pretty quickly
becomes something other than the CPUs. Even if we assume the operating
system issue is solved by making the OS kernel multi-threaded and adding
fine grained locks on shared data structures (which is a difficult
problem,) we are still left with all the hardware components that do not
scale when we add CPUs: notably the bus and the memory which are shared
among all CPUs. Pretty soon adding more processors will not speed the
system at all, given that the main bottlenecks reside elsewhere. This is
why SGI is evolving away from SMP into the new paradigm of cc-NUMA
(Cache-coherent Non Uniform Memory Access), and using a new OS
foundation (Cellular IRIX TM) in its new Origin TM product line. "


Michael