I was reading that with large level 2 caches of 1:1 ratio the main problem
with multiple processors was in caches read/write conflicts, with a large
level 2 cache the amount of time needed to wait for data over the main bus
was reduced, mind you this was from IMB and Motorola and about there
competition to Intels upcoming 64bit chip, so it could be just marketing
propaganda, they plan to basically just stick 4 64bit Power PC processors
in the same chip maybe along with a VLIW processor for DSP, and were
working on new cache page flagging algorithms, I think they were going to
transfer some of the work load to code compilation stage similar to what
Intel plans to do with there knew 64bit EPIC(explicitly parallel
instruction computer, I think this is just marketing talk for VLIW).

I see that the MPEG-4 audio description language seems to be up and running
at  anybody had I go at it, no mac
version yet and I don't plan to touch a line of code until I can get
Rhapsody, though I'm think of just writing my own framework for Rhapsody, I
want to create a framework with the goals of emphasis on non-real time, a
pull instead of push signal model were units request signals instead of
having signals passed to them, the ability for units to request signals
from any point in time(ie look forward/backwards in audio, score or control
paths, I'll add some buffer units to help reduce the doubling up of
calculations), but most importantly just the ability to design instruments
with some smarts, ie instruments that have more abstract controllers/ add
there own accidentals/ fill in details.

Nathan Day
nathand@senet.com.au