| Subject: Re: cacheing
Reply-To: MohrJ@Augustana.AB.CA
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Les Rackl wrote, in reply to Javier Ruiz:
> >P.S. I have just bought a 8600/200, should I buy more cache memory for
> >real time performance? (I have already enough DRAM)
>
>
> >Javier Ruiz
>
>
> If you are loading data into the CPU from RAM in 64K chunks (say), then
> 64K of cache
> can add tremendous performance increases, because it "pre-fetches" the
> data chunk and
> can then load into the CPU very, very quickly (something like 1 CPU
> cycle).
>
> If you're not loading 64K chunks, though, you'll be generating cache
> misses which will actually
> degrade performance, relative to having no cache.
It is theoretically possible (but highly unlikely) that a memory
usage pattern could cause poorer performance using a cache than not
using a cache due to generating a large number of cache misses.
However, research has shown that even rather small cache sizes will
yield a hit ratio above 0.75 (see references in Stallings, "Computer
Organization and Architecture", 4e, p. 154), so it is usually worth
the money to add an L2 cache. (It may not be worth the money to
_increase_ the size of an existing L2 cache, since you do not get
linear improvement in hit ratio with increasing cache size. For
example, if you have a 64K L2 cache already, it may be worth it to
increase that to 128K but may not worth it to go to to 256K. It is
unlikely that anything beyond 512K will be of much use, according to
test results.)
> This is my understanding of it, though i confess to not understanding the
> differences between
> Level 1 and Level 2 cache. Could someone straighten this out for me?
The L1 cache is the cache memory which is placed on the same chip as
the CPU by the chip manufacturer. For example, the 80386 has no
on-chip cache, the 80486 has a single 8 KB cache, and the Pentium has
two on-chip caches -- one for data and one for instructions -- each
of size 8 KB. Since the CPU does not need to access the on-chip
cache via an external bus, and due to the extremely short data paths
on the chip, on-chip cache access is extremely fast.
An L2 cache is a bank of high performance memory which can
optionally be installed on most system boards which the CPU can
access via an external bus. Cache memory is more expensive per bit
than "regular" memory, not only because it is faster but also because
it has to provide a special form of addressing so that caching will
work (typically, a form of what is called "associative" memory).
Because it is off-chip, the size of the L2 cache is user-configurable
(or OEM-configurable), so any debates about which cache sizes are
appropriate, either based on speed or cost factors, are referring to
the L2 cache. (On the other hand, comparisons of various
microprocessors may include discussion of the relative sizes of their
L1 cache memories.)
> les
Regards,
Jonathan Mohr
Jonathan Mohr, Associate Professor of Computing Science
Augustana University College, Camrose, Alberta, Canada T4V 2R3
Phone: (403) 679-1514 Fax: (403) 679-1129
E-mail: MohrJ@Augustana.AB.CA
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From: jpff@maths.bath.ac.uk
Subject: Re: cps2pch Question & Chord Strumming Orc/Sco
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Message written at 18 Nov 1997 22:38:01 +0000
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from Hans Mikelson on Sat, 08 Nov 1997 13:54:16)
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In answer to teh question..
How do you use cps2pch with unequal temperament?
i refer you to the documentation (edited here for simplicity)
icps cps2pch ipch, iequal
Converts a pitch-class notation into cycles-per-second for equal
divisions of the octave.
There is a restriction of no more than 100 equal divisions.
INITIALISATION
ipch - Input number of the form 8ve.pc, indicating an `octave' and
which note in the octave.
iequal - if positive, the number of equal intervals into which the
`octave' is divided. Must be less than or equal to 100.
if negative is the number of a table of frequency multipliers
EXAMPLES
inote cps2pch p5, 19 ; convert oct.pch to cps in 19ET
The use of a table allows exotic scales by mapping frequencies in a table
For example the table
f2 0 16 -2 1 1.1 1.2 1.3 1.4 1.6 1.7 1.8 1.9
can be used with
ip cps2pch p4, -2
to get a 10 note scale of unequal divisions
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From: jpff@maths.bath.ac.uk
Subject: Re: 32-bit float AIFF
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Richard Dobson on Mon, 17 Nov 1997 17:56:39 +0000 (GMT))
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Can you give a reference to what the format is for WAV/float? Without
that it is rather hard to incorporate the format into the main system
==John ff
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Date: Wed, 19 Nov 1997 18:11:58 +0100
From: Khalid
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Hi,
when you say "quoted headers" do you mean
the lines that reference earlier mails and start with
the smaller-than sign? Or do you mean the stuff that
documents the route the mail has travelled and that's
usually on mail that has been sent to several adresses
i a row? Do you have a suggestion how we could ease
the thing for you people?
khalid
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Subject: Re: cacheing
Date: Thu, 20 Nov 97 06:45:30 +1200
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From: Graeme Gerrard
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james@noether.ex.ac.uk
>example, if you have a 64K L2 cache already, it may be worth it to
>increase that to 128K but may not worth it to go to to 256K. It is
>unlikely that anything beyond 512K will be of much use, according to
>test results.)
Below is a message I sent to Javier re this thread.
>I have a 7300/200, but it came with a 256K cache like the 8600. I put in
>a 512K cache but can't remember the speed increase it gave, but I do
>remember it was significant. Soon after, I tested a 1Mb cache
>against 512K with MacBench and found a 16% increase in processor speed.
>There were very few 1M caches around at the time and they were expensive
>so I stayed with the 512K.
I rechecked my figues and it was an 11% increase, not 16%. The increase
from 256K to 512K was much more as I recall. Check on MacWorld or one of
those places - they had a set of results there earlier this year.
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